In order to drive the gates of the semiconductor power switching elements such as IGBTs configuring a power conversion bridge circuit of a conventional power converter such as an industrial inverter, an isolation transformer or a photo coupler is used to create electrical insulation between the controller and the gate driver circuit. In recent years, however, for the purpose of cost reduction, a high voltage integrated circuit device (referred to as “HVIC,” hereinafter) that does not require electrical insulation has been used mainly for lower capacities.
Non-patent Literature 1 and Patent Literature 1, for example, disclose conventional HVICs. Non-patent Literature 1 discloses a HVIC using a self-isolation process employing a bulk substrate. An example of a conventional HVIC 200 using a self-isolation process is shown in FIGS. 26, 27 and 28.
FIG. 26 is a plan view showing substantial parts of the conventional HVIC 200. The HVIC 200 generally has a high-side gate driver circuit 1137, a level up circuit 1140 including Nch level shifters 1132, an input control circuit 1136, and a high voltage junction terminating structure 1130. There are two Nch level shifters 1132, a level shifter for transmitting a set signal and a level shifter for transmitting a reset signal, each of which is a Nch field effect transistor formed integrally with the high voltage junction terminating structure 1130. Letters HI in the diagram means “high level,” LO means “low level,” IN means “input,” and OUT means “output.” A signal at the IN side is based on a GND potential, while a signal at the OUT side is based on a VS potential.
FIG. 27 is a cross-sectional diagram of the substantial parts, taken along line XXVII-XXVII of FIG. 26. In the cross-sectional structure of the conventional HVIC 200, deep n-type diffusion regions, i.e., an n diffusion region 1102 and an n diffusion region 1103, are formed in the front surface of a p-type bulk substrate 1101 (Psub). In addition, the input control circuit 1136 is formed in the front surface of the n diffusion region 1102, and a high-side gate driver circuit 1137 is formed in the front surface of the n diffusion region 1103. The bulk substrate is an original substrate on which the diffusion regions are not yet formed. Relatively shallow p-type diffusion regions, i.e., a p diffusion region 1111 and a p diffusion region 1112 are formed in the front surfaces of the n diffusion region 1102 and the n diffusion region 1103 respectively and partially in order to form the Nch field effect transistors and the like. The p diffusion region 1111 is connected to a ground (GND) terminal, a reference potential of the input control circuit 1136, by a p+ diffusion region 1109. The p diffusion region 1112 is connected to a VS terminal, a reference potential of the high-side gate driver circuit 1137, by a p+ diffusion region 1110. The n diffusion region 1102 is connected to a VCC terminal, a power supply terminal of the input control circuit 1136, by an n+ diffusion region 1107. The n diffusion region 1103 is connected to a VB terminal, a power supply terminal of the high-side gate driver circuit 1137, by an n+ diffusion region 1108. A voltage of 9 V to 24 V, power supply voltage of the high-side gate driver circuit 1137, is applied between the VB terminal and the VS terminal.
A first parasitic diode 1141 and a second parasitic diode 1142 are formed, respectively, in a junction 1102a between the n diffusion region 1102 and the p-type bulk substrate 1101 and a junction 1103a between the n diffusion region 1103 and the p-type bulk substrate 1101.
Hereinafter, the area of the n diffusion region 1103 where the high-side gate driver circuit 1137 is formed is referred to as “high-side circuit region 1135,” and the area of the n diffusion region 1102 where the input control circuit 1136 is formed is referred to as “low-side circuit region 1133.” In other words, the reference numerals 1103 and 1135 represent the identical region, as well as the reference numerals 1102 and 1133.
The high voltage junction terminating structure 1130 is formed around the high-side circuit region 1135, in which a voltage that is equal to or higher than the potential of the low-side circuit region 1133 by approximately 600 V can be applied to the high-side circuit region 1135. The high voltage junction terminating structure 1130 is configured by a double-RESURF structure with an n− diffusion region 1105, which is a light n-type diffusion region, a p diffusion region 1120, which is a shallow p-type diffusion region, and the p-type bulk substrate 1101.
The Nch level shifters 1132 are Nch field effect transistors that are formed integrally with the high voltage junction terminating structure 1130. The components of each Nch level shifter 1132 are: an n− diffusion region 1106 which is deep, light n-type diffusion region configuring a withstand voltage structure and a drain-drift region, a p− diffusion region 1119 which is a shallow p-type diffusion region configuring the high voltage junction terminating structure 1130, an n+ diffusion region 1116 which is a shallow, dark n-type diffusion region configuring the drain, a n+ diffusion region 1115 which is a shallow, dark n-type diffusion region configuring the source, a p diffusion region 1122 which is a relatively shallow, dark p-type diffusion region configuring the channel, a p+ diffusion region 1114 which is a shallow, dark p-type diffusion region configuring a pickup of a back gate, a gate oxide film 1125, and a gate electrode 1124.
In order to form a level up resistor 1127 between the VB terminal and the drain terminal of each Nch level shifter 1132, the n diffusion region 1103 connected to the VB terminal and the n− diffusion region 1106 connected to the drain terminal are electrically isolated from each other by a p− diffusion region 1147.
Note that the n diffusion region 1102 is connected to the VCC terminal by a p+ diffusion region 1121. The VB terminal is connected to the VCC terminal by a bootstrap diode 1129, shown by the dotted line in the diagram. A bootstrap capacitor (a power supply capacitor at the high side) 1138 is connected between the VB terminal and the VS terminal.
FIG. 28 is a representative circuit schematic of the HVIC 200 shown in FIG. 26. Note that the level up circuit 1140 is described only as a set circuit, and a reset circuit is not shown.
An operation of the conventional HVIC 200 for driving a high-side device (high-side power device) of a bridge circuit is described using FIG. 28. As shown in FIG. 27, the VS terminal is connected to a connecting point between a low-side device (low-side power device) and the high-side device that configure the bridge circuit, in which a high-side driver circuit is operated between the VS potential and a VB potential, with the VS potential taken as a reference potential as described above. The VB potential is VS potential+approximately 9 V to 24 V.
A set signal and a reset signal that are input to the input control circuit 1136 are transmitted through the level up circuit 1140 to the high-side gate driver circuit 1137 that is operated based on the VS potential.
When the set signal is transmitted, the gate of the high-side device of the bridge circuit is turned on, and when the reset signal is transmitted, the gate of the high-side device of the bridge circuit is turned off. During the operation of the HVIC 200, the potential of the VS terminal changes between 0 V to several hundred V.
Also, the high-side gate driver circuit 1137 is configured with a buffer circuit R, an Nch field effect transistor, a Pch field effect transistor, and the like.
In the diagram, the alphabet “a” represents the VB terminal connected to the high-potential terminal of the bootstrap capacitor 1138, “b” the VS terminal connected to the low-potential terminal of the bootstrap capacitor 1138, “c” a connecting terminal connected to the anode of the bootstrap diode 1129, “d” an input terminal for ON/OFF signals, “e” the VCC terminal, “f” an output terminal for ON/OFF signals, “g” the VS terminal connected to an intermediate potential point of the bridge circuit, “h” a Psub terminal, and “i” the GND terminal. The h and i are each a single terminal. These terminals are the terminals of the semiconductor device 200. The small black circles represent the connecting points between the circuits, and the small squares represent the connections to the respective circuit regions.
Patent Literature 1 describes that a more stable operation of an integrated circuit can be realized throughout a wide range applied high voltages, by providing a (diffused or polysilicon) level shift resistor in parallel with a resistor Repi of an epitaxial layer without providing a metal cross over for high voltages (metal lines extending from a low-side region to a high-side region).
Patent Literatures 2 and 3 each disclose a method for preventing a parasitic diode from being biased forward and hence preventing a malfunction of the high-side gate driver circuit 1137 by applying a negative bias to a substrate potential through the use of a negative voltage power supply.
Patent Literature 1: Japanese Patent No. 3214818
Patent Literature 2: U.S. Pat. No. 6,211,706 (Specification)
Patent Literature 3: U.S. Pat. No. 6,967,518 (Specification)
Non-patent Literature 1: Proc. of The 11th Int. Symp. On Power Semiconductor Devices and ICs IEEE and IEEJ, 1999, pp. 333-336
In a case where a load connected to the power devices driven by the HVIC 200 (e.g., IGBTs (Insulated Gate Bipolar Transistors) configuring the bridge circuit) is an inductive load, a negative voltage surge where the VS potential drops instantaneously below the GND potential occurs due to counter electromotive force that is generated in the load as soon as the high-side power device is turned off.
When the voltage (absolute value) of the negative voltage surge is greater than the voltage between the VB terminal and the VS terminal, the VB potential also drops below the GND potential, in addition to the VS potential. For instance, when the negative voltage surge is −200 V and the voltage between the VB terminal and the VS terminal is 15 V, the VB potential becomes lower than the GND potential (Psub potential) by 185 V (15 V-200 V).
In the conventional HVIC 200 that uses the self-isolation process described above, the second parasitic diode 1142 is formed between the VB terminal and the GND terminal. When the VB potential drops below the GND potential and the second parasitic diode 1142 is biased forward, causing the voltage thereof to become equal to or greater than a forward voltage of 0.6 V, then electrical conduction occurs in the second parasitic diode 1142. Due to this electrical conduction, a surge current flows from the p-type bulk substrate 1101 (Psub) connected to the GND terminal to the n diffusion region 1103 which is the high-side circuit region 1135 connected to the VB terminal. This surge current causes a malfunction of the high-side gate driver circuit 1137. The tolerance to the negative voltage surge of the conventional HVIC 200 is approximately −200 V. In other words, applying a negative voltage surge within this approximately −200 V prevents a malfunction of the high-side gate driver circuit 1137. This problem also occurs in an HVIC that uses a junction isolation process.
The methods described in Patent Literatures 2 and 3 which prevent forward biasing of the parasitic diode by applying a negative bias to the substrate potential using a negative voltage power supply, require a negative voltage power supply, bringing about a problem that increases the costs significantly.